1. Field of the Invention
The present invention relates to Flash memories, and more particularly a page-erasable Flash memory of the type described by the international application WO 02/41322, comprising means for checking and refreshing memory cells in the programmed state.
2. Description of the Related Art
Flash memory memory cells differ from EEPROM memory memory cells by the fact that they do not comprise access transistors. As a result, in a Flash memory array, the floating-gate transistors of the memory cells are directly linked to the bit lines of the memory array.
Another particular feature of Flash memories is that the memory cells do not have any gate control transistor. As a result, when an erase voltage is applied to a word line, the control gates of all the floating-gate transistors receive this voltage. Therefore, the erasing operation in a Flash memory is a collective operation that affects at least all the memory cells of a same word line (page). For an operation of erasing by the channel, the erasing affects all the memory cells of a same sector (memory cells having a common substrate, formed in a P-type well) unless a selective page-erase method described in the aforementioned international application is implemented.
As their memory cells do not therefore have any access transistor or gate control transistor, Flash memories provide a high density of integration in terms of number of memory cells per unit of silicon surface.
However, this simplification of the structure of the memory cells leads to various disadvantages, particularly a programming stress phenomenon.
The programming of a memory cell is indeed an operation that comprises the application, to a bit line to which the memory cell is linked, of a programming voltage Vpp (drain voltage of the floating-gate transistor). Now, all the floating-gate transistors linked to the bit line in question receive the voltage Vpp since they do not have any access transistor. This leads to an electrical stress called programming stress or drain stress.
This drain stress is particularly problematic in a page-erasable Flash memory of the type described by the aforementioned international application. Indeed, providing a page-erasable Flash memory is only worthwhile if the user is given the possibility of erasing and reprogramming a same page a considerable number of times, without being concerned about the other pages of the memory. Now, when the user applies successive erasing and programming cycles to the memory cells of a same page, the memory cells of the other pages receive the programming voltage repeatedly at their drains, which leads to a gradual alteration of the electric charges trapped in their floating gates and can result in data corruption.
To overcome this disadvantage, the aforementioned international application suggests a program refresh method comprising a step of cyclically checking the pages of the memory, and a step of refreshing the programmed memory cells that have lost electric charges. This refresh involves reprogramming the memory cells and avoids these memory cells gradually switching into the erased state.